Radio frequency switch transistors are required to carry large currents and switch at high speeds. In certain applications, the switches need to operate in the hundreds of gigahertz (GHz) range and handle upwards of one watt of input power in a linear fashion. Traditional transistor technologies such as metal-oxide-semiconductor (MOS) transistors fabricated using doped silicon are able to perform under these operating requirements, but generally consume a large area of a semiconductor wafer and often require exotic processing steps to perform under such stringent conditions.
FIG. 1 illustrates a high level view of a single pole four throw (SP4T) switch 100 implemented using MOS transistors. A main signal bus 101 is independently coupled to four different throws 102-105 via different transistor arrays 106. The transistor arrays 106 comprise multiple fingers of a single transistor. The arrays are relatively large features for an integrated circuit because the width of the transistors needs to be large enough to decrease the on resistance of the transistor to a near negligible level. For comparison, current digital transistors implemented using MOS processing have widths that are on the order of nanometers while the width of the transistor in each transistor array 106 is on the order of millimeters. The same type of transistor technology is therefore being used to form devices that differ in size by a factor of more than a million.
In addition to the strain placed on a transistor technology that has to perform in such widely divergent applications, the size of wafer real estate that is consumed by these transistors weighs heavily on the overall cost of the integrated circuit on which the switch is fabricated. In a typical implementation, the width of each array 106 can be on the order of one millimeter while the height of each array 106 can be on the order of 0.3 millimeters. While these dimensions are not necessarily immense as compared to the die size of certain application specific integrated circuits, any decrease in die array contributes directly to the potential profitability of an integrated circuit design.